Measurement-computing PCI-DIO48H/CTR15 User Manual

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Summary of Contents

Page 1 - User’s Manual

PCI-DIO48H/CTR15Digital I/O & CountersUser’s ManualRevision 2March, 2001

Page 2 - HM PCI-DIO48H-CTR15.lwp

state). We recommend using 2.2 K SIPs on the digital output pins. You will findpositions for pull up and pull down resistor packs on the board. For mo

Page 3 - Table of Contents

5 I/O REGISTER MAPSThe PCI-DIO48H/CTR15 uses eight standard I/O addresses for the two 8255emulations, 20 addresses for the five 82C54s (4 each) as wel

Page 4 - This page is blank

5.1 PCI-DIO48H/CTR15 REGISTER DESCRIPTIONINTERRUPT STATUS/CONTROLBADR1 + 4ChREAD/WRITEINTEINTPOLINTxxxxxx0123456731:8This register, as with all the 90

Page 5 - 2 INSTALLATION

CONTROL REGISTER 1BADR2 + 03hWRITE onlyD0D1-D3D4---01234567The operating mode of the digital I/O ports is Mode 0. The control register thereforeis us

Page 6 - 2.2 HARDWARE

PORT 2C DATABADR2 + 06hREAD/WRITECL0CL1CL2CL3CH0CH1CH2CH301234567CONTROL REGISTER 2BADR2 + 07hWRITE onlyD0D1-D3D4---01234567See BADR2 + 03h and Table

Page 7 - 3 I/O CONNECTIONS

First the low byte is written, then the high byte. The Control Register is 8-bits wide.Further information can be obtained on the 82C54 data sheet, av

Page 8

COUNTER 9 DATABADR2 + 12hREAD/WRITED0D1D2D3D4D5D6D701234567CONTROL REGISTER COUNTERS 7 - 9BADR2 + 13hWRITE ONLYD0D1D2D3D4D5D6D701234567See BADR2 + 0Ch

Page 9

COUNTER 13 DATA BADR2 + 18hREAD/WRITED0D1D2D3D4D5D6D701234567COUNTER 14 DATA BADR2 + 19hREAD/WRITED0D1D2D3D4D5D6D701234567COUNTER 15 DATABADR2 + 1AhRE

Page 10 - 4 SOFTWARE

6 SPECIFICATIONSTypical for 25°C unless otherwise specified. POWER CONSUMPTION+5V Operating 1395 mA typical, 2091 mA maxDIGITAL INPUT/OUTPUTDigital T

Page 11 - 5 I/O REGISTER MAPS

82C54B:Counter 0 - User counter #4Source: Available at user connector (CTR4CLK)Gate: Available at user connector (CTR4GATE)Output: Available at user

Page 12

MEGA-FIFO, the CIO prefix to data acquisition board model numbers, the PCM prefix to dataacquisition board model numbers, PCM-DAS08, PCM-D24C3, PCM-DA

Page 13

Counter 1 - User counter #14Source: Available at user connector (CTR14CLK)Gate: Available at user connector (CTR14GATE)Output: Available at user conn

Page 14

7 ELECTRONICS AND INTERFACINGThis short introduction to the electronics, most often needed by digital I/O boardusers, covers a few key concepts.IMPORT

Page 15

Of course, a pull-down resistor accomplishes the same task except that the line ispulled low when the board is reset and the output has more than enou

Page 16

SSRs. If you have only a few outputs to control, you may also wish to consider theDR-OAC or DR-ODC, single point, DIN mountable SSRs. The high current

Page 17

For a given attenuation, pick a handyresistor and call it R2, then use thisformula to calculate R1.R1 = (A−1) x R2Digital inputs often require voltage

Page 19

For Your Notes22

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EC Declaration of ConformityWe, Measurement Computing Corporation, declare under sole responsibility that theproduct:DescriptionPart NumberDigital I/O

Page 21 - 7 ELECTRONICS AND INTERFACING

Measurement Computing Corporation16 Commerce Boulevard,Middleboro, Massachusetts 02346(508) 946-5100Fax: (508) 946-9500E-mail: info@measurementcomputi

Page 22 - 7.2 TTL TO SOLID STATE RELAYS

Table of Contents217.3 VOLTAGE DIVIDERS ...207.2 TTL TO SOLID STATE RELAYS ...197.1 PULL UP &

Page 24

1 INTRODUCTIONThe PCI-DIO48H/CTR15 is a multifunction, logic level, digital I/O board forcomputers that implement the PCI bus. The board offers a powe

Page 25 - For your notes

InstaCal will show you any available options. It will create a configuration file thatyour application software (and the Universal Library) will refer

Page 26 - For Your Notes

3 I/O CONNECTIONS3.1 CONNECTOR DIAGRAMThe 100-pin, high-density connector is accessible through the computer’s expansionbracket (Figure 3-1). The outp

Page 27

The I/O connections can be brought out to easy-to-use screw terminals by purchasinga CFF100-series cable and two CIO-MINI50 screw terminal boards. The

Page 28

See Figure 3-3 for a translation diagram of the upper half (pins 51 to 100) of theC100FF-xx cable to the second 50-pin connector.Figure 3-3. C100FF-xx

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