Measurement-computing CIO-DAS08-PGH User Manual Page 24
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4.10 TRIGGER & INTERRUPT LOGIC
The trigger logic on the CIO-DAS08-PGx is quite simple. Pin 24 of the 37 pin connector is an input to a flip-flop which can be
read at BASE address + 2 on the IRQ bit. The board can be triggered by polling this bit until a trigger pulse (rising edge) has
occurred. It must be reset by a write to BASE + 2 before it will respond to additional rising edges.
By writing a 1 to the INTE control bit at BASE + 2, the rising edge detected by the flip-flop will be translated into an interrupt
pulse which can be used to interrupt the CPU's 8259 interrupt controller on the PC motherboard.
The interrupt level jumper on the board may need to be installed. Move it from the 'X' (default) position to the IRQ number you
want the interrupt pulse on.
The 82C54 counter/timer chip is primarily a pacer for A/D samples. It is an integral part of the trigger logic. To employ the 82C54
as an A/D pacer, wire the output of the counter (pin 6) that you will program to provide pacing pulses directly into the Interrupt
Input (pin 24).
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- Revision 9 1
- October, 2000 1
- HM CIO-DAS08PGx.lwp 2
- This page is blank 4
- 1: INTRODUCTION 5
- 1.2 HARDWARE INSTALLATION 6
- 2: SIGNAL CONNECTION 8
- 3: ANALOG CONNECTIONS 9
- 3.2 WIRING CONFIGURATIONS 13
- A/D Board 14
- 4: REGISTER ARCHITECTURE 17
- 4.2 A/D DATA REGISTER 18
- 4.6 COUNTER CONTROL REGISTER 21
- 4.7 COUNTER/TIMER 22
- 4.8 DIGITAL INPUT 23
- 4.9 DIGITAL OUTPUT 23
- 5: SPECIFICATIONS 25
- Counter section 26
- Environmental 26
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